loop lock
英 [luːp lɒk]
美 [luːp lɑːk]
网络 环阻
双语例句
- The loop is a second order phase lock loop, consisting of an interpolator, a timing error detector and a loop filter.
环路为反馈结构，包括插值器、时钟误差检测和环路滤波器三个部分。 - We begin our discussion with a description of an imbalance OQPSK model, then analyze the effect on carrier tracking loop steady-state lock point and the effect on average BEP.
通过对OQPSK调制器不均衡的模型讨论，深刻分析了调制器不均衡对载波跟踪环路稳态锁定点和平均BEP的影响。 - GPS/ INS integration systems are widely used in different fields. Since GPS receiver carrier loop has lost lock during maneuver, the velocity aiding signal of code loop is derived from the inertial navigation system.
GPS／惯性导航组合系统目前正得到越来越广泛的应用，但GPS接收机载波环失锁时，码环的速率辅助信息来自惯导系统。 - The error model of the GPS receiver code loop can be expressed as the Markovian process. When GPS receiver carrier loop loses lock, the velocity aiding signal of the code loop is derived from the inertial navigation system.
GPS接收机码环跟踪回路的误差模型一般可用一阶马尔可夫过程来近似，且当接收机载波环路失锁时，码环的速率辅助信息来自惯性导航系统的惯性速度。 - The New Measurement Method of Open Loop Frequency Response for PLL Under Lock State
锁相环在锁定状态下测试开环频率特性的新方法 - The paper analyses the system operation principle and the design of phase lock loop. Simultaneously, the paper proposes the control block of the system and phase lock loop program flow chart.
文中详细分析了系统的工作原理和锁相环设计，同时给出了系统的控制框图和锁相环程序流程图，并进行了样机实验。 - A digital phase-locked loop ( DPLL) based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range, low jitter, and fast acquisition.
提出了一种数字锁相环（DPLL），它的相频检测器采用全新的设计方法和自校准技术，具有工作频率范围宽，抖动低，快速锁定的优点。 - The zero-crossing PLL i.e.hardware PLL, is comprised of PFD ( Phase-Frequency Detector), loop filter, VCO ( Voltage Control Oscillator) and frequency divider. It is really simple but poor in dynamic performance, and even worse in phase lock effect with distorted input voltage.
过零锁相即硬件锁相（PLL）由鉴相器、环路滤波器、压控振荡器及分频器组成，其原理和结构较简单，但动态性能较差，且在畸变电压输入时锁相效果变差； - According the existed problems in high frequency power supply development, it presented feasibility of fulfilling the high frequency power supply used the matured power electronics technology and phase loop lock control based on improved resonant topology LLC upgrade from LC resonant topology.
根据目前国内外高频感应加热电源发展中存在的问题，提出采用的LLC谐振拓扑，利用比较成熟的电力电子技术和锁相环控制设计完成高频感应加热电源。 - In the outer control loop, a proportional integral voltage controller is used to regulate the CD-link voltage. A phase lock loop circuit is adopted to generate a sinusoidal waveform in phase with main voltage to achieve power factor correction.
控制电路采用两个控制回路：外部控制回路用比例积分电压控制器调整直流环节电压，采用相位闭环电路产生与电源电压同相的正弦波形来实现功率因数补偿。 - Study of loop of delay lock phase
延迟锁相环的研究 - The simulation results show that the locking loop of DTG on moving base can lock DTG nearby the zero deflection angle during the whole course from rest to working and to rest again.
仿真表明：此动基座锁定回路能够较好地将动力调谐陀螺仪在静止→正常工作→静止的整个过程中都能锁定在零偏角附近。 - The coherent delay lock loop is shown to have a major advantage, for a relatively high fading bandwidth, it has a zero tracking error, while a noncoherent delay lock loop has bias error of up to ten of meters.
对于大的衰减带宽，相干延迟锁定环路的多径跟踪误差为零，而非相干延迟所定环路有10m左右误差，载波相位的测量无误差； - Because of the basic feature of self-bias PLL, the ratio of loop bandwidth and reference clock can be kept to be a certain range so that both of the lock time and input tracking jitter can be improved.
因为自偏置锁相环的特点，使得所设计的锁相环的带宽与输入频率的比值可以保持在一个相对稳定的范围，对锁定时间以及输入频率跟踪抖动得到改善。 - Main performance index of the phase-locked loop lock is short time, small synchronous error, suitable frequency.
锁相环的主要性能指标是锁定时间短、同步误差小，适用频带适当。 - Delay-Locked Loop ( DLL) has been widely used in various timing systems because of its features of fast lock time and no sensitive to jitter.
延迟锁相环（Delay-LockedLoop，DLL）因具备时钟定位准确、抗抖动能力强、锁定速度快等优点，在各种时序系统中得到了广泛应用。 - The phase-locked loop frequency synthesizer is a kind of phase lock installment and it is a kind of separate gap frequency code generator with high stability frequency.
锁相环频率合成器是一种相位锁定装置，是一种频率稳定度较高的离散间隔型频率信号发生器。 - Delay phase ‐ locked loop compared to phase lock loop, has characteristics of better stability, smaller clock jitter.
延时锁相环与锁相环相比，具有更好的稳定性，更小的时钟抖动等特点。 - While introducing the phase-locked loop circuit design, equipment of PFD, charge pump, variable loop filter, divider circuit and out of lock detection circuit design are also given detailed descriptions.
锁相环设计又详细介绍了鉴频鉴相器、电荷泵、可变环路滤波器、分频电路以及失锁检测电路的设计。 - The locking behavior of the PLL and the reasons that might cause the loop to become out of lock are studied and verified by simulation.
对注入锁定PLL的锁定过程进行研究，分析了可能引起失锁的原因，并通过电路仿真进行了验证。 - In the input interface circuit, contrived all digital phase-locked loop ( ADPLL) with high accuracy which can exactly track and lock the frequency of power grid, in order to meet integer-cycle sampling or reduce the degree of non-integer-cycle sampling, so decrease measurement error.
在输入接口电路中，设计高精度全数字锁相环实现对电网频率进行精密跟踪锁定，使得达到整周期采样或减小非整周期采样的程度以减小测量误差。 - Focus on discussing the trace loop based on Delay Lock Loop ( DLL), improve the accuracy of phase detecting by Least Squares.
在跟踪方法上重点讨论了基于延迟锁相环的跟踪环路，给出了其实现方案，并利用最小二乘法提高鉴相精度。 - If the traditional structure and algorithms are used to track the signal, it must increase loop bandwidth to remain locked. But this would increase the loop noise which can also cause the tracking loop losing lock.
如果采用传统的算法和结构进行跟踪，那么要想保持锁定就必须增加环路滤波器的带宽，但是这样会使进入环路的噪声增大，造成跟踪环失锁。 - When the system is in burst mode, so long as the loop is locked, the locked frequency value is saved in LPF ( Low Pass Filter) of PLL ( Phase Lock Loop).
当系统工作于突发模式时，只要环路有锁定的情况发生，则锁定的频率点将保存在环路滤波电容中，保证了对于有效信号组信号相位的快速锁定。